1. Field of the Invention
The present invention relates to a booster circuit which is used in a non-volatile semiconductor memory or a semiconductor integrated circuit.
2. Description of the Related Art
Recently, in a flash memory serving as a non-volatile storage device, it is required to read and rewrite data at single power supply voltage or low power supply voltage. Therefore, when the individual operations are performed, a booster circuit for supplying a boosting voltage or a negative boosting voltage is needed on chip.
FIGS. 10 and 11 are block diagrams illustrating the configuration of a booster circuit according to the related art.
The configuration of FIGS. 10 and 11 will be described. The booster circuit is configured by a plurality of booster cells 901 that are connected in series. Each of the booster cells 901 includes a charge transfer transistor M3, a switching transistor M2, a gate voltage boosting capacitor C1, and an output-voltage capacitor C2. The charge transfer transistor M3 transfers charges from the preceding stage to the following stage. The switching transistor M2 equalizes a gate voltage Vg of the charge transfer transistor M3 with a drain voltage Vd at the preceding stage so as to have the same potential. The gate voltage boosting capacitor C1 equalizes the gate voltage Vg of the charge transfer transistor M3 with the drain voltage Vd and then pumps up the gate voltage Vg to be synchronized with a clock CLKS such that the charge transfer transistor M3 is turned on. The output-voltage capacitor C2 turns on the charge transfer transistor M3 in accordance with the clock CLKS and then pumps up a source voltage Vs in accordance with a clock signal CLKM. FIG. 10 shows an example in which four stage booster cells 901 are connected in series. As the booster cells 901 pump up a power supply voltage Vdd, charges are transferred to the following stage, and an-output voltage Vpp is output through the reverse flow prevention circuit M1.
FIG. 12 shows four-phase clock signals CLK1 to CLK4 connected to the last stage booster cell 5 (901) and the operational states of the switching transistor M2 and the charge transfer transistor M3.
The last stage booster cell 4 receives the clock signals CLK2 and CLK3, and the charge transfer transistor M3 is turned on to be synchronized with the clock signal CLK2 so as to transfer charges from the preceding stage to the following stage, and to equalize the drain voltage Vd and the gate voltage Vg. Similarly, in the booster cells 2n (n is an integer equal to or larger than 1), the charge transfer transistor M3 is controlled to be synchronized with the clock signal CLK2, and the switching transistor M2 is driven to be synchronized with the clock signal CLK3. In the booster cells 2n−1 (n is an equal to or larger than 1), the charge transfer transistor M3 is controlled to be synchronized with the clock signal CLK1, and the switching transistor M2 is controlled to be synchronized with the clock signal CLK4.
The operation of the booster circuit configured in such a manner will be described hereinafter with reference to FIG. 13. FIG. 13 shows four-phase clock signals CLK1 to CLK4, the respective terminal voltages and an output voltage Vpp of the charge transfer transistor of the last stage booster cell 4.
When the clock signal CLK3 is H, the booster cell 4 equalizes the drain voltage Vd and the gate voltage V of the charge transfer transistor M3 through the switching transistor M2. Next, as the clock signal CLK3 is set to L, the booster cell 4 enters in a high-impedance (Hiz) state, while maintaining the high gate voltage Vg of the charge transfer transistor M3. As the clock signal CLK2 is changed to H from L, the booster cell 4 pumps up the gate voltage Vg to turn on the charge transfer transistor M3. Accordingly, the charge of the drain is transferred to the source. After the charge is transferred, the clock signal CLK2 is set to L, and the charge transfer transistor M3 is turned off. Then, as the clock signal CLK3 is changed to H from L, the source voltage Vs is further pumped up. Accordingly, the boosted voltage Vpp is output to the output terminal. In the state where the boosted voltage Vpp has been output, if the operation mode is switched over from the rewrite mode to the read mode, the output voltage Vpp transits from a high voltage to a low voltage.
At this time, the voltage levels of the source voltage Vs and the drain voltage Vd of the charge transfer transistor M3 decrease as the output voltage Vpp drops down. However, there is a case where the gate voltage Vg remains at the Hiz state depending on the timing of the clock signal CLK2 such that a high voltage is maintained. When the gate voltage Vg is a high voltage, the charge transfer transistor M3 is turned on. Accordingly, although the clock signal CLK3 is changed to H from L, the charge flows back from the source to the drain through the charge transfer transistor M3, and thus the source voltage Vs cannot be pumped up.
The above problem may be also occurred when the operation mode transits from the rewrite mode, where the boosted voltage Vpp is output, to the STOP mode when the boosted voltage returns back to the power supply voltage, as shown in FIG. 14. At the read mode as the following transition mode, pumping efficiency decreases so that the significantly long recovery time is needed in the booster circuit.
In order to solve the above-described problem, Japanese Patent No. 3670642 has proposed a booster circuit.
FIGS. 15 to 17 show an example of the configuration shown in Japanese Patent No. 3670642.
Reference numeral 902 represents a booster cell provided with a reset circuit which pulls out a gate voltage of the charge transfer transistor in accordance with a gate voltage reset signal ACTR, and corresponds to the booster cell 901. Reference numeral 903 represents a voltage reset circuit which pulls out the charge of the gate voltage Vg of the charge transfer transistor to Vdd or higher in accordance with the gate voltage reset signal ACTR. The voltage reset circuit 903 is composed of diode-connected transistors M4, MS, and M6, which are provided in consideration of potential difference at the time of pulling out a charge, and a transistor M7 which is controlled in accordance with the gate voltage reset signal ACTR. Moreover, like reference numerals represent the same components as those of the above-described booster circuit.
An example of the circuit operation of the booster circuit of Japanese Patent No. 3670642 will be described.
When a boosting operation is performed by four-phase clock signals CLK1 to CLK4, the gate voltage reset signal ACTR is L. The booster cell 902 transfers a charge from the preceding stage to the following stage and performs a boosting operation, similar to the booster cell 901.
As shown in FIG. 18, when the operation mode of the booster circuit transits from the rewrite mode when the boosted voltage is high to the read mode when the boosted voltage is low, the gate voltage reset signal ACTR becomes H. Accordingly, the voltage reset circuit becomes in an operation state such that the gate voltage Vg of the charge transfer transistor is transited from a high voltage to a low voltage. As the gate voltage Vg of the charge transfer transistor is lowered, the charge transfer transistor can be turned off even though the operation mode transits to the read mode when the boosted voltage is low. Therefore, typical pump-up can be performed at the source voltage Vs, and the operation of the booster circuit can be stably performed. Similarly, this is also performed when the operation mode transits from the rewrite mode through the STOP mode to the read mode in FIG. 19. The voltage reset circuit is a unit which is useful in the mode conversion where the operation mode transits from the state where the boosted voltage Vpp is high to the state where the boosted voltage Vpp is low.
In the conventional booster circuit using the booster cell 902, however, the gate voltage Vg of the charge transfer transistor is always lowered when the gate voltage reset signal is H. Therefore, there is a case when the gate voltage Vg becomes lower than the source voltage Vs. In the STOP state, for example, the output voltage Vpp becomes the power source voltage Vdd, and the source voltage Vs also becomes the power source voltage Vdd. However, the gate voltage Vg becomes lower than the power source voltage Vdd. If the gate voltage Vg becomes lower than the source voltage Vs, the switching transistor M2 is turned on. Then, an electric current flows from the drain to the switching transistor M2 through the respective transistors M4 to M7 of the voltage reset circuit 903 such that consumed current or stop current at the time of operation transition increases.
Further, if the gate voltage Vg is excessively pulled out, the time (equalization time) when the drain voltage Vd and the gate voltage Vg are averaged so as to be held at the same potential through the switching transistor M2 immediately after the mode transition becomes insufficient. Further, the charge transfer transistor is not sufficiently turned on, the charge transfer efficiency decreases, and the recovery time of the booster circuit is lengthened.